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TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91CY22IFG
Preface
Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0 to 4, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP91CY22I
CMOS 16-Bit Microcontrollers
TMP91CY22IFG 1. Outline and Features
TMP91CY22I is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91CY22I comes in a 100-pin flat package. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4-channels (593 ns/2 bytes at 27 MHz)
(2) Minimum instruction execution time: 148 ns (at 27 MHz) (3) Built-in RAM: 16 Kbytes Built-in ROM: 256 Kbytes
RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
030619EBP
* The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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(4) External memory expansion * * Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus ... Dynamic data bus sizing
(5) 8-bit timers: 8 channels (6) 16-bit timer/event counter: 2 channels (7) General-purpose serial interface: 2 channels UART/ Synchronous mode: 2 channels IrDA ver1.0 (115.2 kbps) supported (8) Serial bus interface: 1 channel * I2C bus mode/clock synchronous Select mode (9) 10-bit AD converter: 8 channels (10) Watchdog timer (11) Special timer for CLOCK (12) Chip Select/Wait controller: 4 channels (13) Interrupts: 45 interrupts * * * 9 CPU interrupts: Software interrupt instruction and illegal instruction 26 internal interrupts: 10 external interrupts: Seven selectable priority levels
(14) Input/Output ports: 81 pins (15) Standby function Three HALT modes: IDLE2 (programmable), IDLE1, STOP (16) Triple-clock controller * * * * * * Clock Doubler (DFM) Clock Gear (fc to fc/16) SLOW mode (fs = 32.768 kHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz) VCC = 1.8 V to 3.6 V (fc max = 10 MHz) 100-pin QFP: P-LQFP100-1414-0.50F
(17) Operating voltage
(18) Package
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D V C C [3] D V S S [3] X1 X2
EMU0 EMU1 XT 1 (P 9 6) XT 2 (P 9 7)
R ESET
A D T R G (P 53 ) A N 0 to A N 7 (P 50 to P 57)
C P U (T L C S -9 0 0 /L 1 )
AVCC, AVSS V RE FH, V RE FL
10 -B it 8C H AD C on ve rter
T XD 0 (P 9 0) R XD 0 (P 9 1)
S C LK 0/ C T S 0 (P 92 )
S IO /U A R T /IrD A
XW A XB C XDE XHL XIX XIY XIZ XS P
(S IO 0)
S IO /U A R T (S IO 1)
S eria l B us In terfac e (S B I)
T XD 1 (P 93) R XD 1 (P 94)
S C LK 1/ C T S 1 (P 95 )
A C E L IX IY IZ SP 32 bits SR F PC
W B D H
H -O S C
C lo c k G e a r C loc k d o u b le r
L-O S C
AM0 AM1 ALE
P ort 0
P ort 1
S C K (P 6 0) S O /S D A (P 6 1) S I / S C L (P 6 2)
W atc h dog T im e r (W D T )
P ort 2
T A 0 IN (P 70)
T A 1O U T (P 71)
8-B it T im er (T M R A 0 )
8-B it T im er (T M R A 1 )
8-B it T im er (T M R A 2 )
S pec ial tim er for C LO C K
P ort 3
(P 00 to P 0 7) A D 0 to A D 7 (P 10 to P 17 ) A D 8/A 8 to A D 15/A 15 (P 20 to P 27 ) A 0 /A 1 6 to A 7/A 23 R D (P 30) W R (P 31) H W R (P 32) B U S R Q (P 3 4) B U S A K (P 3 5) R / W (P 36) P37
(P 64 ) S C O U T , P 65, P 6 6 P A 4 to P A 7
(P 40 to P 43 )
P ort 6
P o rt A
C S /W A IT
T A 3O U T (P 72)
8-B it T im er (T M R A 3 )
16 -K B R A M
T A 4 IN (P 73)
T A 5O U T (P 74)
8-B it T im er (T M R A 4 )
8-B it T im er (T M R A 5 )
8 -B it Tim er (T M R A 6 )
C o n tro lle r (4-B L O C K )
Inte rru pt C o n tro lle r
C S 0 to
W A IT
CS3
(P 33)
NMI IN T 0 (P 6 4) IN T 1 to 4 (P A 0 to 3 )
T B 0 IN 0 /IN T 5 (P 8 0) T B 0 IN 1 /IN T 6 (P 8 1) T B 0 O U T 0 (P 82) T B 0 O U T 1 (P 83) T B 1 IN 0 /IN T 7 (P 8 4) T B 1 IN 1 /IN T 8 (P 8 5) T B 1 O U T 0 (P 86) T B 1 O U T 1 (P 87)
25 6-K B R O M
16 -B it T im er (T M R B 0 )
16 -B it T im er (T M R B 1 )
T A 7O U T (P 75)
8-B it T im er (T M R A 7 )
(
): Initial func tion afte r re s et
Figure 1.1 TMP91CY22I Block Diagram
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2.
Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91CY22I, their names and functions are as follows:
2.1
Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91CY22I.
88 P65 DVCC P66 DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3/ADTRG P54/AN4 P55/AN5 P56/AN6 P57/AN7 VREFH VREFL AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/TA7OUT P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RX1 P95/SCLK1/CTS1 AM0 DVCC X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 EMU0 EMU1 PA0/INT1 PA1/INT2 PA2/INT3 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 87 P64/SCOUT 86 P63/INT0 85 P62/SI/SCL 84 P61/SO/SDA 83 P60/SCK 82 P43/CS3 81 P42/CS2 80 P41/CS1 79 P40/CS0 78 P37 77 P36/R/W 76 P35/BUSAK 75 P34/BUSRQ 74 P33/WAIT 73 P32/HWR 72 P31/WR 71 P30/RD 70 P27/A7/A23 69 P26/A6/A22 68 P25/A5/A21 67 P24/A4/A20 66 P23/A3/A19 65 P22/A2/A18
LQFP100 Top View
64 DVCC 63 NMI 62 DVSS 61 P21/A1/A17 60 P20/A0/A16 59 P17/AD15/A15 58 P16/AD14/A14 57 P15/AD13/A13 56 P14/AD12/A12 55 P13/AD11/A11 54 P12/AD10/A10 53 P11/AD9/A9 52 P10/AD8/A8 51 P07/AD7 50 P06/AD6 49 P05/AD5 48 P04/AD4 47 P03/AD3 46 P02/AD2 45 P01/AD1 44 P00/AD0 43 ALE 42 PA7 41 PA6 40 PA5 39 PA4 38 PA3/INT4
Figure 2.1.1 Pin assignment diagram (100-pin LQFP)
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2.2
Pin Names and Functions
The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions. Table 2.2.1 Pin names and functions (1/4)
Pin Name
P00 to P07 AD0 to AD7 P10 to P17 AD8 to AD15 A8 to A15 P20 to P27 A0 to A7 A16 to A23 P30
RD
Number of Pins
8 8
I/O
I/O Tri-state I/O Tri-state Output I/O Output Output
Functions
Port 0: I/O port that allows I/O to be selected at the bit level Address and data (lower): Bits 0 to 7 of address and data bus Port 1: I/O port that allows I/O to be selected at the bit level Address and data (upper): Bits 8 to 15 for address and data bus Address: Bits 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: Bits 0 to 7 of address bus Address: Bits 16 to 23 of address bus Port 30: Output port Read: Strobe signal for reading external memory RD is outputted by setting P3 = 0 and P3FC < P30F> = 1, when reading internal area. Port 31: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port 32: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins AD8 to AD15 Port 33: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait ((1 + N) wait mode) Port 34: I/O port (with pull-up resistor) Bus Request: Signal used to request that set AD015, A023, RD , WR , HWR ,
R/W
8
1
Output Output
P31
WR
1 1 1 1
Output Output I/O Output I/O Input I/O Input I/O Output
P32
HWR
P33
WAIT
P34
BUSRQ
, CS0 CS3 pins to High impedance. (For external DMAC)
P35
BUSAK
1
Port 35: I/O port (with pull-up resistor) Bus Acknowledge: Signal used to acknowledge that AD015, A023, RD , WR , HWR , R / W , CS0 CS3 pins are set to High impedance by receiving BUSRQ . (For external DMAC) Port 36: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 37: I/O port (with pull-up resistor) Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 if address is within specified address area Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 if address is within specified address area Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 if address is within specified address area
P36
R/W
1 1 1
I/O Output I/O I/O Output I/O Output I/O Output I/O Output
P37 P40
CS0
P41
CS1
1 1 1
P42
CS2
P43
CS3
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Table 2.2.1 Pin names and functions (2/4) Pin Name
P50 to P57 AN0 to AN7
ADTRG
Number of Pins
8
I/O
Input Input Input I/O I/O I/O Output I/O I/O Input I/O I/O Input I/O Output I/O I/O I/O Input I/O Output I/O Output I/O Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output I/O Input Input I/O Input Input I/O Output I/O Output
Functions
Port 5: Pin used to input port Analog input: Pin used to input to AD converter AD Trigger: Signal used to request start of AD converter (Shared with P53) Port 60: I/O port Serial bus interface clock in SIO Mode Port 61: I/O port Serial bus interface output data in SIO Mode Serial bus interface data in I2C bus Mode. (programmable open-drain) Port 62: I/O port Serial bus interface input data in SIO Mode Serial bus interface clock in I2C bus Mode. (programmable open-drain) Port 63: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge Port 64: I/O port System Clock Output: Outputs fFPH or fs clock. Port 65: I/O port Port 66: I/O port Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 71: I/O port 8-bit timer 1 output:Timer A1 Output Port 72: I/O port 8-bit timer 3 output: Timer A3 Output Port 73: I/O port 8-bit timer 4 input:Timer A4 Input Port 74: I/O port 8-bit timer 5 output:Timer A5 Output Port 75: I/O port 8-bit timer 7 output:Timer A7 Output Port 80: I/O port 16-bit timer 0 input0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. Port 81: I/O port 16-bit timer 0 input1: Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 Port 84: I/O port 16-bit timer 1 input0: Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16-bit timer 1 input 1: Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1
P60 SCK P61 SO SDA P62 SI SCL P63 INT0 P64 SCOUT P65 P66 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 TA7OUT P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1
1 1
1
1
1 1 1 1 1 1 1 1 1 1
1
1 1 1
1
1 1
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Table 2.2.1 Pin names and functions (3/4) Pin Name
P90 TXD0 P91 RXD0 P92 SCLK0
CTS0 P93 TXD1 P94 RXD1 P95 SCLK1 CTS1 P96 XT1 1 1 1 1
Number of Pins
1 1
1
I/O
I/O Output I/O Input
I/O I/O Input I/O Output I/O Input I/O I/O Input I/O Input
Functions
Port 90: I/O port Serial Send Data 0 (programmable open-drain) Port 91: I/O port Serial Receive Data 0
Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 (programmable open-drain) Port 94: I/O port Serial Receive Data 1 Port 95: I/O port Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port (open-drain output) Low-frequency oscillator connection pin
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Table 2.2.1 Pin names and functions (4/4) Pin Name
P97 XT2 PA0 to PA3 INT1 to INT4 PA4 to PA7 ALE
NMI
Number of Pins
1 4
I/O
I/O Output I/O Input Port 97: I/O port (open-drain output)
Functions
Low-frequency oscillator connection pin Ports A0 to A3: I/O ports Interrupt Request Pins 1 to 4: Interrupt request pins with programmable rising edge / falling edge. Ports A4 to A7: I/O ports Address Latch Enable (Can be disabled to reduce noise.) Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Operation mode: Fixed to AM1 = "1", AM0 = "1". Set to Open pins Reset: initializes TMP91CY22. (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter Power GND pin for AD converter (0 V)
4 1 1 2 1 1 1 1 1 1 2 3 3
I/O Output Input Input Output Input Input Input
AM0 to AM1 EMU0/EMU1
RESET
VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS Note:
I/O
High frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.)
An external DMA controller cannot access the device's built-in memory or built-in I/O devices using the BUSRQ and
BUSAK signal.
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3.
Operation
This device is a version of expanding its internal mask ROM size to 256 Kbytes and RAM size to 16 Kbytes. The configuration and the functionality of this device are the same as those of the TMP91CW12A. For the functions of this device that are not described here, refer to the TMP91CW12A data sheet.
3.1
Memory Map
Figure 3.1.1 is a memory map of the TMP91CY22I.
000000H
Internal I/O (4 Kbytes)
Direct area (n)
000100H 001000H Internal RAM (16 Kbytes) 005000H
64 Kbyte area (nn)
010000H
External memory
FC0000H
Internal ROM (256 Kbytes)
16 Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn)
FFFF00H FFFFFFH
Vector Table (256 bytes) ( = Internal area)
Figure 3.1.1 Memory Map
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4.
4.1
Electrical Characteristics
Maximum Ratings
Parameter
Power Supply Voltage Input Voltage Output Current Output Current Output Current (total) Output Current (total) Power Dissipation (Ta = 85C) Soldering Temperature (10 s) Storage Temperature Operating Temperature
Symbol
Vcc VIN IOL IOH IOL IOH PD TSOLDER TSTG TOPR
Rating
-0.5 to 4.0 -0.5 to Vcc + 0.5 2 -2 80 -80 600 260 -65 to 150 -40 to 85
Unit
V V mA mA mA mA mW C C C
Note:
The maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no maximum rating value will ever be exceeded.
Point of note about solderability of lead free products (attach "G" to package name)
Test parameter Solderability Test condition (1) Use of Sn-63Pb solder Bath Solder bath temperature =230C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder bath Solder bath temperature =245C, Dipping time = 5 seconds The number of times = one, Use of R-type flux (use of lead free) Note Pass: solderability rate until forming 95%
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4.2
DC Characteristics (1/2)
Parameter Symbol
VCC
Condition
fc = 4 to 27 MHz fc = 2 to 10 MHz Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V
Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V IOL = 1.6 mA IOL = 0.4 mA IOH = -400 A IOH = -200A Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V
Min
2.7
Typ. (Note)
Max
3.6
Unit
V
Power Supply Voltage (AVcc = DVcc) (AVss = DVss = 0 V) P00 to P17 (AD0 to 15) P20 to PA7 (except P63)
RESET , NMI , P63 (INT0)
fs = 30 to 34 kHz
1.8 0.6 0.2Vcc 0.3Vcc 0.2Vcc -0.3 0.25Vcc
0.15Vcc 0.3 0.3 0.2Vcc 0.1Vcc 2.0 0.7Vcc 0.7Vcc 0.8Vcc 0.75Vcc 0.85Vcc Vcc - 0.3 Vcc - 0.3 0.8Vcc 0.9Vcc 0.45 0.15Vcc 2.4 0.8Vcc V Vcc + 0.3 V
VIL VIL1
VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH
Input Low Voltage Input High Voltage
Note:
AM0, 1 X1 P00 to P17 (AD0 to AD15) P20 to PA7 (except P63)
RESET , NMI , P63 (INT0)
AM0, 1 X1
Output Low Voltage Output High Voltage
Typical values are for when Ta = 25C and Vcc = 3.0 V unless otherwise noted.
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4.2
DC Characteristics (2/2)
Parameter Symbol
ILI ILO VSTOP RRST CIO VTH
Condition
0.0 VIN Vcc 0.2 VIN Vcc - 0.2 V IL2 = 0.2 Vcc, V IH2 = 0.8 Vcc Vcc = 3 V 10% Vcc = 2 V 10% fc = 1 MHz Vcc 2.7 V Vcc < 2.7 V Vcc = 3 V 10% Vcc = 2 V 10% Vcc = 3 V 10% fc = 27 MHz Vcc = 2 V 10 % fc = 10 MHz (Typ.: Vcc = 2.0 V) Vcc = 3 V 10 % fs = 32.768 kHz Ta 70C Ta 85C Vcc = 2 V 10 % fs = 32.768 KHz (Typ.: Vcc = 2.0 V) Vcc = 1.8 to 3.3V
Min
Typ. (Note 1)
0.02 0.05
Max
5 10
3.6 400 1000 10
Unit
A
V k pF V
Input Leakage Current Output Leakage Current Power Down Voltage (at STOP, RAM back-up)
1.8 100 200 0.4 0.3 100 200 10.0 2.5 1.0 1.7 0.6 0.25 11.6 5.2 3.0 7.7 3.5 2.0 0.1 1.0 0.8
RESET Pull-up Resistor
Pin Capacitance Schmitt Width
RESET , NMI , INT0
Programmable Pull-up Resistor NORMAL (Note 2) IDLE2 IDLE1 NORMAL (Note 2) IDLE2 IDLE1 SLOW (Note 2) IDLE2 IDLE1 SLOW (Note 2) IDLE2 IDLE1 STOP Note 1: Note 2:
RKH Icc
400 1000 13.0 3.5 1.8 2.5 0.9 0.4 30 19 8 15 20 13 10 10 mA mA k
A
A A
Typical values are for when Ta = 25C and Vcc = 3.0 V unless otherwise noted. Icc measurement conditions (NORMAL, SLOW): All functions are operating; output pins are open and input pins are fixed.
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4.3
AC Characteristics
(1) Vcc = 3.0 V 10% Variable Min
37.0 0.5x - 14 0.5x - 16 x - 20 0.5x - 14 0.5x - 10 x - 10 x - 23 1.5x - 26 0.5x - 13 x - 13 3.0x - 38 3.5x - 41 2.0x - 30 2.0x - 15 0 x - 15 1.5x - 15 1.5x - 35 x - 25 3.5x - 60 3.0x - 50 2.0x + 0 3.5x - 89 3.5x 3.5x + 80 129 209 74 40 59 0 22 40 20 12 69 61
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Parameter
fFPH Period ( = x) A0 to A15 Vaild ALE Fall ALE Fall A0 to A15 Hold ALE High Width ALE Fall RD / WR Fall
Symbol
tFPH tAL tLA tLL tLC tCLR tCLW tACL tACH tCAR tCAW tADL tADH tRD tRR tHR tRAE tWW tDW tWD
1+n wait Mode 1+n wait Mode 1+n wait Mode
fFPH = 27 MHz Min
37.0 4 2 17 4 8 27 14 29 5 24 73 88 44
Max
31250
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RD Rise ALE Rise WR Rise ALE Rise
A0 to A15 Valid RD / WR Fall A0 to A23 Valid RD / WR Fall
RD Rise A0 to A23 Hold WR Rise A0 to A23 Hold
A0 to A15 Valid D0 to D15 Input A0 to A23 Valid D0 to D15 Input
RD Fall D0 to D15 Input
RD Low Width
RD Rise D0 to A15 Hold RD Rise A0 to A15 Output
WR Low Width
D0 to D15 Valid WR Rise
WR Rise D0 to D15 Hold
A0 to A23 Valid WAIT Input A0 to A15 Valid WAIT Input
tAWH tAWL tCW tAPH tAPH2 tAP
RD / WR Fall WAIT Hold
A0 to A23 Valid Port Input A0 to A23 Valid Port Hold A0 to A23 Valid Port Valid
AC Measuring Conditions * Output Level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF * Input Level: High = 0.9 Vcc, Low = 0.1 Vcc
Note:
"x" used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of "x" changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear=1/fc (SYSCR1 = 0000).
91CY22I-13
2005-06-21
TMP91CY22I
(2) Vcc = 2.0 V 10% No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Parameter
fFPH Period ( = x) A0 to A15 ALE Fall ALE Fall A0 to A15 Hold ALE High Width ALE Fall RD / WR Fall
Symbol
tFPH tAL tLA tLL tLC tCLR tACW tACL TACH tCAR TCAW tADL tADH TRD tRR tHR tRAE tWW tDW tWD
1+n wait mode 1+n wait mode 1+n wait mode
Variable Min
100 0.5 x - 28 0.5 x - 35 x - 40 0.5x - 28 0.5x - 20 x - 20 x - 75 1.5x -70 0.5x - 30 x - 30 3.0x - 76 3.5x - 82 2.0x - 60 2.0x - 30 0 x - 30 1.5 x - 30 1.5 x - 70 x - 50 3.5x - 120 3.0x - 100 2.0x + 0 3.5x - 170 3.5x 3.5x + 170
fFPH =10M Hz Min
100 22 15 60 22 30 80 25 80 20 70 224 268 140 170 0 70 120 80 50 230 200 200 180 350 520
Max
31250
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
RD Rise ALE Rise WR Rise ALE Rise
A0 to A15 Valid RD / WR Fall A0 to A23 Valid RD / WR Fall
RD Rise A0 to A23 Hold WR Rise A0 to A23 Hold
A0 to A15 Valid D0 to D15 Input A0 to A23 Valid D0 to D15 Input
RD Fall D0 to D15 Input RD Low Width RD Rise D0 to D15 Hold RD Rise A0 to A15 Output WR Low Width
D0 to D15 Valid WR Rise
WR Rise D0 to D15 Hold
A0 to A23 Valid WAIT Input A0 to A15 Valid WAIT Input
tAWH tAWL tCW tAPH tAPH2 tAP
RD / WR Fall WAIT Hold
A0 to A23 Valid Port Input A0 to A23 Valid Port Hold A0 to A23 Valid Port Valid
AC Measuring Conditions * Output Level: High = 0.7 Vcc, Low = 0.3 Vcc, CL = 50 pF * Input Level: High = 0.9 Vcc, Low = 0.1 Vcc Note: "x" used in an expression shows a frequency for the clock fFPH selected by SYSCR1. The value of "x" changes according to whether a clock gear or a low-speed oscillator is selected. An example value is calculated for fc, with gear=1/fc (SYSCR1 = 0000).
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2005-06-21
TMP91CY22I
(3) Read Cycle
tFPH
fFPH
A0 to A23
CS0 to CS3
R/W
tAWH tAWL
tCW
WAIT
tAP Port input (Note) tACH tAC tLC AD0 to AD15 A0 to A15 tAL ALE tLL tLA tAPH2 tADH tCAR tRR tRAE tHR D0 to D15 tCLR
RD
tRD tADL
Note:
Since the CPU accesses the internal area to read data from a port, the control signals of external pins such as RD and CS
are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
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2005-06-21
TMP91CY22I
(4) Write Cycle
fFPH
A0 to A23
CS0 to CS3
R/W
WAIT
tAP Port Output (Note)
WR, HWR
tCAW tWW tDW tWD
AD0 to AD15
A0 to A15
D0 to D15 tCLW
ALE
Note:
Since the CPU accesses the internal area to write data to a port, the control signals of external pins such as WR and CS are not enabled. Therefore, the above waveform diagram should be regarded as depicting internal operation. Please also note that the timing and AC characteristics of port input/output shown above are typical representation. For details, contact your local Toshiba sales representative.
91CY22I-16
2005-06-21
TMP91CY22I
4.4
AD Conversion Characteristics
AVcc = Vcc, AVss = Vss parameter Symbol
VREFH VREFL
Condition
Vcc = 3 V 10% Vcc = 2 V 10% Vcc = 3 V 10% Vcc = 2 V 10%
Min
Vcc - 0.2 V Vcc Vss Vss VREFL
Typ.
Vcc Vcc Vss Vss
Max
Vcc Vcc Vss + 0.2 V Vss VREFH
Unit
V
Analog Reference Voltage (+) Analog Reference Voltage (-)
Analog Input Voltage Range VAIN Analog Current for Analog Reference Vcc = 3 V 10% Voltage IREF = 1 Vcc = 2 V 10% (VREFL = 0V) Vcc = 1.8 V to 3.3 V = 0 Error (not including quantizing errors) Note 1: Note 2: Note 3:
0.94 0.65 0.02
1.20 mA 0.90 5.0
A
LSB
-
Vcc = 3 V 10% Vcc = 2 V 10%
1.0 1.0
4.0 4.0
1 LSB = (VREFH - VREFL)/1024 [V] The operation above is guaranteed for fFPH 4 MHz. The value for ICC includes the current which flows through the AVCC pin.
91CY22I-17
2005-06-21
TMP91CY22I
4.5
Serial Channel Timing (I/O Internal Mode)
(1) SCLK Input Mode
Parameter
SCLK Period Output Data SCLK Rising /Falling Edge* SCLK Rising/Falling Edge*
Symbol
tSCY
Variable Min
16X tSCY/2 - 4x -110 (Vcc=3V10%) tSCY/2 - 4x -180 (Vcc=2V10%) tSCY/2 + 2X + 0 3x+10 tSCY - 0 0
10 MHz
27 MHz
Unit
s
Max
Min
1.6 290 220 1000 310
Max
Min
0.59 38
Max
tOSS
ns
370 121 1600 592 0 ns ns ns ns
Output Data Hold
SCLK Rising/Falling Edge*
tOHS tHSR tSRD tRDS
Input Data Hold
SCLK Rising/Falling Edge*
Valid Data Input
Valid Data Input
SCLK Rising/Falling Edge* *) SCLK Rinsing/Falling Edge:
0
The rising edge is used in SCLK Rising Mode. The falling edge is used in SCLK Falling Mode.
Note: Value of 27 MHz and 10MHz at tSCY = 16X.
(2) SCLK Output Mode
Parameter
SCLK Period
Symbol Min
tSCY 16X
Variable Max
8192X
10 MHz
27 MHz
Unit
s
ns ns ns
Min
1.6 760 760 0
Max
819
Min
0.59 256 256 0
Max
303
Output Data tOSS SCLK Rising/Falling Edge* SCLK Rising/Falling Edge*
tSCY/2 - 40 tSCY/2 - 40 0 tSCY - 1X - 180 1X + 180
Output Data Hold
SCLK Rising/Falling Edge*
tOHS tHSR tSRD
Input Data Hold
SCLK Rising Rising/Falling Edge*
Valid Data Input
1320 280 217
375
ns ns
Valid Data Input tRDS SCLK Rising/Falling Edge*
tSCY SCLK Output Mode/ Input Mode SCLK (Input Mode) OUTPUT DATA TXD INPUT DATA RXD
tOSS 0
tOHS 1 tSRD 0 Valid tRDS 1 Valid tHSR 2 Valid 3 Valid 2 3
91CY22I-18
2005-06-21
TMP91CY22I
4.6
Event Counter (TA0IN, TA4IN, TB0IN0, TB0IN1, TB1IN0, TB1IN1)
Parameter
Clock period Clock Low level width Clock High level width
Symbol
tVCK tVCKL tVCKH
Variable Min
8X + 100 4X + 40 4X + 40
10 MHz
27 MHz
Unit
ns ns ns
Max
Min
900 440 440
Max
Min
396 188 188
Max
4.7
Interrupt and Capture
(1) NMI , INT0 to INT4 Interrupts
Parameter
NMI , INT0 to INT4 Low level width NMI , INT0 to INT4 High level width
Symbol
tINTAL tINTAH
Variable Min
4X + 40 4X + 40
10 MHz Min
440 440
27 MHz Min
188 188
Unit
ns ns
Max
Max
Max
(2) INT5 to INT8 Interrupts, Capture The INT5 to INT8 input width depends on the system clock and prescaler clock settings.
tINTBL tINTBH System Clock Prescaler Clock (INT5 to INT8 Low level Width) (INT5 to INT8 High Level Width) Unit Selected Selected Variable fFPH = 10 MHz Variable fFPH = 27 MHz
Min 0 (fc) 1 (fs) Note: 00 (fFPH) 10 (fc/16) 00 (fFPH) 8X + 100 128Xc + 0.1 8X + 0.1 Min 396 4.8 244.3 Min 8X + 100 128Xc + 0.1 8X + 0.1 Min 396 4.8 244.3 ns
s
Xc = Period of Clock fc
4.8
SCOUT Pin AC Characteristics
Parameter
Low level width High level width
Symbol
tSCH tSCL
Variable Min
0.5T - 13 0.5T - 25 0.5T - 13 0.5T - 25
10 MHz Min
37 25 37 25
27 MHz Min
5
Max
Max
Max
Condition Unit
Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V ns ns
-
5
-
Note:
T = Period of SCOUT
Measrement Condition
* Output Level: High 0.7 Vcc/Low 0.3 Vcc, CL = 10pF
tSCH tSCL SCOUT
91CY22I-19
2005-06-21
TMP91CY22I
4.9
Bus Request/Bus Acknowledge
BUSRQ
BUSAK
(Note 1)
tCBAL tBAA
AD0 to AD15 A0 to A23, RD , WR
tABA
(Note 2)
(Note 2)
CS0 to CS3 , R / W HWR
ALE
Variable Paramter
Output Buffer Off to BUSAK Low
BUSAK
Symbol Min
tABA tBAA 0 0 0 0
fFPH = 10 MHz Min
0 0 0 0
fFPH = 27 MHz Min
0 0 0 0
Condition Unit
Vcc 2.7 V Vcc < 2.7 V Vcc 2.7 V Vcc < 2.7 V
Max
80 300 80 300
Max
80 300 80 300
Max
80 300 80 300 ns
High
to
Output
Buffer On Note 1:
ns
Even if the BUSRQ Signal goes Low, the bus will not be released while the WAIT signal is Low. The bus will only be released when BUSRQ goes Low while WAIT is High.
Note 2:
This line shows only that the output buffer is in the Off state. It does not indicate that the signal level is fixed. Just after the bus is released, the signal level set before the bus was released is maintained dynamically by the external capacitance. Therefore, to fix the signal level using an external resister during bus release, careful design is necessary, since fixing of the level is delayed. The internal programmable pull-up/pull-down resistor is switched between the active and non-active states by the internal signal.
91CY22I-20
2005-06-21
TMP91CY22I
4.10 Recommended Oscillation Circuit
TMP91CY22I has been evaluated by murata manufacturing Co., Ltd. Please refer to murata manufacturing Co., Ltd.
Note:
Total loads value of oscillator is sum of external loads (C1 and C2) and floating loads of actual assemble board. There is a possibility of miss-operating. When designing board, it should design minimum length pattern around oscillator. And we recommend that oscillator evaluation try on your actual using board.
(1) Examples of resonator connection
X1 X2 XT1 XT2
Rd
Rd
C1
C2
C1
C2
Figure 4.10.1 High-frequency Oscillator Connection
Figure 4.10.2 Low-frequency Oscillator Connection
(2) Recommended ceramic resonators for TMP91CY22I: Murata Manufacturing Co., Ltd.
Ta = -40 to 85C Parameter of Oscillation MCU Frequency [MHZ] Item of Oscillator C1 [pF] 2.00 4.00
TMP91CY22I
Elements C2 [pF] (47) (39) (47) (39) (47) (15) 0 Rd []
Running Condition Voltage of Power [V] 1.8 2.2 Tc[C]
CSTCC2M00G56-R0 CSTCR4M00G55-R0 CSTLS4M00G56-B0 CSTCR6M75G55-R0 CSTLS6M75G56-B0 CSTLS10M0G53-B0
(47) (39) (47) (39) (47) (15)
2.7 3.3
-20 +80
6.00 10.00
1.8 2.2
* *
In CST*** type oscillator, capacitance C1, C2 is built-in. The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following URL; http://www.murata.co.jp
91CY22I-21
2005-06-21
TMP91CY22I
5.
Package Dimensions
P-LQFP100-1414-0.50F Unit: mm
91CY22I-22
2005-06-21

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